The field of the invention relates to data processing and in particular to register renaming in a processing apparatus.
It is known to provide data processing apparatus which process instructions from an instruction set that specifies registers using an architectural set of registers, while the apparatus itself uses a physical set of registers that is larger than the architectural set. This is a technique that has been developed to try to avoid resource conflicts due to instructions executing out of order in the processor. In order to have compact instruction encodings most processor instruction sets have a small set of register locations that can be directly named. These are often referred to as the architecture registers and in many ARM® (registered trade mark of ARM Ltd Cambridge UK) RISC instruction sets there will be 32 architecture registers.
When instructions are processed different instructions take different amounts of time to complete. In order to speed up execution times, processors may have multiple execution units, and may perform out of order execution. This can cause problems if the data used by these instructions is stored in a very limited register set as a value stored in one register may be overwritten before it is used by another instruction. This leads to errors. In order to address this problem it is known for some processing cores to perform processing using more registers than are specified in the instruction set. Thus, for example, a core may have 56 physical registers to process an instruction set having 32 architecture registers. This enables a core to store values in more registers than is specified by the instruction set and can enable a value needed by an instruction that takes a long time to be executed to be stored in a register not used by other neighbouring instructions. In order to be able to do this the core needs to “rename” the registers referred to in the instruction set so that they refer to the physical registers in the core. In other words an architectural register referred to in the instruction is mapped onto a physical register that is actually present on the core.
Renaming of the registers is generally done using a renaming table which maps registers from the architecture set of registers to registers in the physical set. The renaming occurs early in the processing pipeline generally shortly after decode and it is important that the mapping is kept until the instruction has completed and any other instruction that needs to read from the register written to has also completed. However, at a certain point the physical register that was mapped to the architectural register will need to be released so that it can be used in another mapping otherwise the processor will run out of physical registers to map to. Generally a set of conditions are applied that when met indicate that a mapping is no longer required and the physical register can be released. The conditions include that the register write has been performed and that the mapping is no longer in the renaming table. There are further conditions that are required in processors where exceptions may occur to ensure that the processor can be restarted following an exception, thus, the mappings that were current at a point where speculative execution starts need to be stored in a restore table and the physical registers present in this table should not be remapped until it is known that the speculatively executed instructions will complete. An exception may occur where instructions are executed speculatively and it is determined that the prediction that triggered the execution was not correct. Non-exception instructions are instructions that execute in a statically determined way such that it is known that they will complete.
Further problems may arise for source registers of store instructions which may have a very long latency if the store misses at the address translation level, where a virtual address is translated to a physical address, whereupon the instruction may remain stalled for a long time during which time the physical register used to hold the value that is to be written to memory must not be overwritten by another instruction thus, it must not be available for renaming. This is addressed using a “snapshot” where a record of source registers for pending stores is kept and the state of the processor core monitored, the register renaming circuitry avoids renaming these registers until it is determined that the store has completed.
Thus, the conditions for freeing renamed registers are in cases complex and can lead to registers being unavailable for a significant amount of time. It would be desirable to be able to identify situations where registers do not need to meet all of these conditions such that they can be freed more quickly and easily.